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quad if receiver data sheet AD6657A rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their resp ective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all ri ghts reserved. features 11- bit, 200 msps output data rate per channel integrated noise shaping requantizer performance with nsr enabled snr: 76.0 dbfs in 40 mhz band to 70 mhz at 185 msps snr: 73.6 dbfs in 60 mhz band to 70 mhz at 185 msps snr: 72.8 dbfs in 65 mhz band to 70 mhz at 185 msps performance with nsr disabled snr: 66.5 dbfs to 70 mhz at 185 msps sfdr: 88 dbc to 70 mhz at 185 msps low power: 1.2 w at 185 msps 1.8 v analog supply operation 1 .8 v lvds (ansi - 644 levels) output 1- to - 8 integer clock divider internal adc voltage reference 1.75 v p - p analog input range (programmable to 2.0 v p - p) differential analog inputs with 800 mhz bandwidth 95 db channel isolation/crosstalk serial port control user - configurable built - in self test (bist) capability energy saving power - down modes applications communications diversity radio and smart antenna (mimo) systems multimode digital receivers (3g) wcdma, lte, cdma2000 wimax, td - scdma i/q demodulation syste ms general - purpose software radios functional block dia gram figure 1 . general description the AD6657A is an 11 - bit, 200 msps, quad channel intermediate frequency (if) receiver specifically designed to support multiple antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. the device consists of four high performance adcs and nsr digi tal blocks. each adc consists of a multistage, differential pipelined architecture with integrated output error correction logic. the adc features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. an integrated voltage reference eases design considerations. a duty cycle stabilizer (dcs) compensates for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. each adc output is connected internally to an nsr bl ock. the integrated nsr circuitry allows for improved snr performance in a smaller frequency band within the nyquist bandwidth. the device supports two different output modes selectable via the external mode pin or the serial port interface ( spi ). with the nsr feature enabled, the outputs of the adcs are processed suc h that the AD6657A supports enhanced snr per - formance within a limited portion of the nyquist bandwidth while maintaining an 11 - bit output resoluti on. the nsr block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sample clock. for example, with a sample clock rate of 185 msps, the AD6657A can achieve up to 76.0 dbfs snr for a 40 mhz bandwidth in the 22% mode, up to 73.6 dbfs snr for a 60 mhz bandwidth in the 33% mode, or up to 72.8 dbfs snr for a 65 mhz bandwidth in the 36% mode. ( general description continued on page 3 ) vin+a doab d10ab vin?a pipeline adc noise shaping requantizer vin+b vin?b pipeline adc vin+c vin?c pipeline adc vin+d vin?d pipeline adc serial port reference 14 11 noise shaping requantizer port a AD6657A port b data multiplexer and lvds drivers 14 11 noise shaping requantizer 14 11 noise shaping requantizer clock divider 09684-001 14 11 vcma vcmb vcmc vcmd sclk sdio csb clk+ avdd agnd drvdd drgnd clk? docd dcoab dcocd d10cd mode sync pdwn
AD6657A data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 product highlights ........................................................................... 3 specifications ..................................................................................... 4 dc specificati ons ......................................................................... 4 ac specifications .......................................................................... 5 digital specifications ................................................................... 7 switching specifications .............................................................. 9 timing specifications ................................................................ 10 absolute maximum ratings ..................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 equivalent circuits ......................................................................... 18 theory of operation ...................................................................... 19 adc architecture ...................................................................... 19 analog input considerations .................................................... 19 clock input considerations ...................................................... 21 power dissipation and standby mode ..................................... 23 channel/chip synchronization ................................................ 23 digital outputs ........................................................................... 24 timing ......................................................................................... 24 noise shaping requantizer ........................................................... 25 22% bw mode (>40 mhz at 184.32 msps) ........................... 25 33% bw mode (>60 mhz at 184.32 msps) ........................... 26 36% bw mode (>65 mhz at 184.32 msps) ........................... 27 mode pin ................................................................................... 27 built - in self test (bist) and output test ................................... 28 bist .............................................................................................. 28 output test modes ..................................................................... 28 serial port interface (spi) .............................................................. 29 configuration using the spi ..................................................... 29 hardware interface ..................................................................... 29 memory map .................................................................................. 30 reading the memory map register table ............................... 30 memory map register table ..................................................... 31 memory map register descriptions ........................................ 33 applications information .............................................................. 35 design guidelines ...................................................................... 35 packaging and ordering information ......................................... 36 outline dimensions ................................................................... 36 ordering guide .......................................................................... 36 revision history 10/11 revision 0: initial version
data sheet AD6657A rev. 0 | page 3 of 36 with the nsr block disabled, the adc data is provided directly to the out put with a resolution of 11 bits. the AD6657A can achieve up to 66.5 dbfs snr for the entire nyquist bandwidth when operated in this mode. this allows the AD6657A t o be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are used. after digital signal processing, multiplexed output data is routed into two 11 - bit output ports such that the maximum digital data rate (ddr) is 400 mbps. these outputs are set at 1.8 v lvds and support ansi - 644 levels. the AD6657A receiver digitizes a wide spectrum of if frequencies. each receiver is designed for simultaneous reception of a separate antenna. t his if sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. flexible power - down options allow significant power savings. programming for device setup and control is accomplished using a 3 - wire spi - compatible serial interface with numerous modes to support board level system testing. the AD6657A is available in a pb - free, rohs compliant, 144- ball , 10 mm 10 mm chip scale package ball grid array (csp_bga) that is specified over the industrial temperature range of ?40c to +85c. product highlights 1. four analog - to - digital converters (adcs) are contained in a small, space - saving, 10 mm 10 mm 1.4 mm, 144 -ball csp_bga package. 2. pin selectable noise shaping requantizer (nsr) function that allows for improved snr within a reduced bandwidth of up to 65 mhz at 185 msps. 3. lvds digital output interface configured for low cost fpga families. 4. 230 mw per adc c ore power consumption. 5. operation from a single 1.8 v supply. 6. standard spi that supports various product features and functions, such as data formatting (offset binary or twos complement), nsr, power - down, test modes, and voltage reference mode. 7. on- chip int eger 1 - to - 8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.
AD6657A data sheet rev. 0 | page 4 of 36 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, f s = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and default spi, unless otherwise noted. table 1. parameter temperature min typ max unit resolution full 11 bits accuracy no missing codes full guaranteed offset error full ?0.9 +0.1 +0.9 mv gain error full +4 +11 +18 % fsr differential nonlinearity (dnl) 1 full ?0.4 0.1 +0.4 lsb integral nonlinearity (inl) 1 ful l ? 0.55 0.17 +0.55 lsb matching characteristic offset error full ?5 +3 +11 mv gain error full 0 +2.1 +8 % fsr temperature drift offset error full 2 ppm/c gain error full 40 ppm/c analog input input range full 1.4 1.75 2.0 v p -p input common - mode voltage full 0.95 v input resistance (differential) full 20 k input capacitance 2 full 5 pf power supplies supply voltage avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v supply current i avdd 1 ful l 466 510 ma i drvdd 1 (1.8 v lvds) ful l 170 183 ma power consumption sine wave input 1 full 1145 1247 mw standby power 3 full 129 mw power - down power full 3.8 10 mw 1 measured with a 10 mhz, 0 db fs sine wave, with 100 termination on each lvds output pair. 2 input capacitance refers to the effective capacitance between one differential input pin and agnd. 3 standby power is measured with a dc input and the clkx pins inactive (set to avdd or agnd).
data sheet AD6657A rev. 0 | page 5 of 36 ac specifications avdd = 1.8 v, drvdd = 1.8 v, f s = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and default spi, unless otherwise noted. table 2. parameter 1 temperature min typ max unit signal - to - noise - ratio (snr) nsr disabled f in = 10 mhz 25c 66.6 dbfs f in = 50 mhz 25c 66.5 dbfs f in = 70 mhz 25c 66.5 dbfs f in = 170 mhz 25c 66.3 dbfs full 65.6 dbfs f in = 250 mhz 25c 65.9 dbfs signal - to - noise - ratio (snr) nsr enabled 22% bw mode f in = 10 mhz 25c 76.0 dbfs f in = 50 mhz 25c 75.7 dbfs f in = 70 mhz 25c 75.7 dbfs f in = 170 mhz 25c 74.3 dbfs full 72.9 dbfs f in = 250 mhz 25c 72.8 dbfs 33% bw mode f in = 10 mhz 25c 73.6 dbfs f in = 50 mhz 25c 73.6 dbfs f in = 70 mhz 25c 73.3 dbfs f in = 170 mhz 25c 72.5 dbfs full 71.3 dbfs f in = 230 mhz 25c 71.2 dbfs 36% bw mode f in = 10 mhz 25c 72.8 dbfs f in = 50 mhz 25c 72.6 dbfs f in = 70 mhz 25c 72.6 dbfs f in = 170 mhz 25c 71.8 dbfs full 70.7 dbfs f in = 250 mhz 25c 70.8 dbfs signal - to - noise - and distortion (sinad) f in = 10 mhz 25c 65.5 dbfs f in = 50 mhz 25c 65.5 dbfs f in = 70 mhz 25c 65.5 dbfs f in = 170 mhz 25c 65.3 dbfs full 64.6 dbfs f in = 250 mhz 25c 64.8 dbfs effective number of bits (enob) f in = 10 mhz 25c 10.6 bits f in = 50 mhz 25c 10.6 bits f in = 70 mhz 25c 10.6 bits f in = 170 mhz 25c 10.6 bits f in = 250 mhz 25c 10.5 bits
AD6657A data sheet rev. 0 | page 6 of 36 parameter 1 temperature min typ max unit worst second or third harmonic f in = 10 mhz 25c ?94 dbc f in = 50 mhz 25c ?91 dbc f in = 70 mhz 25c ?88 dbc f in = 170 mhz 25c ?90 dbc full ?80 dbc f in = 250 mhz 25c ?83 dbc spurious - free dynamic range (sfdr) f in = 10 mhz 25c 94 dbc f in = 50 mhz 25c 91 dbc f in = 70 mhz 25c 88 dbc f in = 170 mhz 25c 90 dbc full 80 dbc f in = 250 mhz 25c 83 dbc worst other harmonic (fourth through eighth) f in = 10 mhz 25c ?94 dbc f in = 50 mhz 25c ?95 dbc f in = 70 mhz 25c ?94 dbc f in = 170 mhz 25c ?94 dbc full ?80 dbc f in = 250 mhz 25c ?90 dbc two tone sfdr (?7 dbfs) f in1 = 169 mhz, f in2 = 172 mhz 25c 89 dbc crosstalk 2 full 95 db analog input bandwidth 25c 800 mhz 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 crosstalk is measured at 155 mhz with ?1 dbfs on one channel and no input on the alternate channel.
data sheet AD6657A rev. 0 | page 7 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, f s = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and default spi, unless otherwise noted. table 3. parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common - mode bias full 0.9 v differential input voltage full 0.2 3.6 v p -p input voltage range full agnd ? 0.3 avdd + 0.2 v high level input voltage full 1.2 2.0 v low level input voltage full 0 0.8 v high level input current full ?10 +10 a low level input current full ?10 +10 a input resistance full 8 10 12 k input capacitance full 4 pf sync input logic compliance cmos internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ?100 +100 a low level input current full ?100 +100 a input resistance full 12 16 20 k input capacitance full 1 pf logic input (csb) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 40 132 a input resistance full 26 k input capacitance full 2 pf logic input (sclk) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?92 ?135 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 2 pf logic input/output (sdio) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 38 128 a input resistance full 26 k input capacitance full 5 pf
AD6657A data sheet rev. 0 | page 8 of 36 parameter temperature min typ max unit logic input (mode) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 40 132 a input resistance full 26 k input capacitance full 2 pf logic input (pdwn) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?90 ?134 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 5 pf digital outputs (lvds) differential output voltage (v od ) full 247 454 mv output offset voltage (v os ) full 1.125 1.375 v 1 pull up. 2 pull down.
data sheet AD6657A rev. 0 | page 9 of 36 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, f s = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and default spi, unless otherwise noted. table 4. parameter temperature min typ max unit clock input parameters input clock rate full 625 mhz conversion rate 1 full 40 185 200 msps clk pulse width high (t ch ) 2 full 2.7 ns aperture delay (t a ) 2 full 1.3 ns aperture uncertainty (jitter, t j ) full 0.13 ps rms data output parameters data propagation delay (t pd ) 2 full 3.0 4.0 4.9 ns dco propagation delay (t dco ) 2 full 3.1 4.0 4.9 ns dco to data skew (t skew ) 2 full ?41 +6.1 +33 ns pipeline delay (latency) full 9 cycles with nsr enabled full 12 cycles wake - up time (from standby) 3 full 0.5 s wake - up time (from power down) 3 full 310 s out - of - range recovery time full 2 cycles 1 conversion rate is the clock rate after the divider. 2 see figure 2 for details. 3 wake - up time is dependent on the value of the decoupling capacitors. data output timing diagram igure data output timing (timing for channel c and channel d is identical to timing for channel a and channel ) n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n clk+ clk? dco+ dco? d10+ab (msb) d10?ab (msb) d0+ab (lsb) d0?ab (lsb) vin t a t ch t dco t cl t pd t skew 1/ f s d10 a d10b d10 a d10b d10 a d10b d10 a d10b d10 a d10b d10 a d10b d0 a d0b d10 a d10b d0 a d0b d0 a d0b d0 a d0b d0 a d0b d0 a d0b d0 a d0b 09684-002
AD6657A data sheet rev. 0 | page 10 of 36 timing specification s avdd = 1.8 v, drvdd = 1.8 v, f s = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and default spi, unless otherwise noted. table 5. parameter description min typ max unit sync timing requirements see figure 3 for details t ssync sync to rising edge of clk setup time 0.24 ns t hsync sync to rising edge of clk hold time 0.40 ns spi timing requirements see figure 60 for details, except where noted t ds setup time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high sclk pulse width high 10 ns t low sclk pulse width low 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not pictured in figure 60 ) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not pictured in figure 60 ) 10 ns sync input timing diagram igure 3 snc input timing reuirements sync clk+ t hsync t ssync 09684-003
data sheet AD6657A rev. 0 | page 11 of 36 absolute maximum ratings table 6. parameter rating avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v vin+x, vin?x to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v sync to agnd ?0.3 v to avdd + 0.2 v vcmx to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to drvdd + 0.2 v sclk to agnd ?0.3 v to drvdd + 0.2 v sdio to agnd ?0.3 v to drvdd + 0.2 v pdwn to agnd ?0.3 v to drvdd + 0.2 v mode to agnd ?0.3 v to drvdd + 0.2 v digital outputs to agnd ?0.3 v to drvdd + 0.2 v dco+ab, dco?ab, dco+cd, dco?cd to agnd ?0.3 v to drvdd + 0.2 v operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +150c thermal characteristics the values in table 7 are per jedec jesd51-7 and jedec jesd25-5 for a 2s2p test board. typical ja is specified for a 4-layer printed circuit board (pcb) with a solid ground plane. as shown in table 7, airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . table 7. package type airflow velocity ja 1 jc 2 jb 3 unit 144-ball csp_bga 0 m/s 26.9 8.9 6.6 c/w 1 m/s 24.2 c/w 2.5 m/s 23.0 c/w 1 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 2 per mil-std 883, method 1012.1. 3 per jedec jesd51-8 (still air). the values in table 8 are from simulations. the pcb is a jedec multilayer board. thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations. table 8. package type airflow velocity ? jb ? jt unit 144-ball csp_bga 0 m/s 14.4 0.23 c/w 1 m/s 14.0 0.50 c/w 2.5 m/s 13.9 0.53 c/w esd caution stresses abo v ethose listedunderabsolutemaximumratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximumratingconditionsfor extendedperiodsmayaffect de v ice reliability.
AD6657A data sheet rev. 0 | page 12 of 36 pin configuration an d function description s figure 4 . pin configuration (top view) table 9 . pin function descriptions pin no. mnemonic type description a5, a8, b5 to b8, d4 to d9, e2 to e11 avdd supply analog power supply. 1.8 v nominal. a1, a4, a9, a12, b1, b2, b4, b9, b11, b12, c2, c3, c10, c11, d3, d10, e1, e12, f1 to f12 agnd ground analog ground. h1 to h12 drvdd supply digital output driver supply. 1.8 v nominal. g1 to g12 drgnd ground digital output driver ground. a7 clk+ input adc clock input true. a6 clk? input adc clock input complement. c12 vin+a input differential analog input pin (+) for channel a. d12 vin?a input differential analog input pin (?) for channel a. d11 vcma output common - mode level bias output for analog input channel a. a11 vin+b input differential analog input pin (+) for channel b. a10 vin?b input differential analog input pin (?) for channel b. b10 vcmb output common - mode level bias output for analog input channel b. a2 vin+c input differential analog input pin (+) for channel c. a3 vin?c input differential analog input pin (?) for channel c. b3 vcmc output common - mode level bias output for analog input channel c. c1 vin+d input differential analog input pin (+) for channel d. d1 vin?d input differential analog input pin (?) for channel d. d2 vcmd output common - mode level bias output for analog input channel d. k7 d0+ab output channel a and channel b lvds output data 0 true. j7 d0?ab output channel a and channel b lvds output data 0 complement. m7 d1+ab output channel a and channel b lvds output data 1 true. l7 d1?ab output channel a and channel b lvds output data 1 complement. k8 d2+ab output channel a and channel b lvds output data 2 true. j8 d2?ab output channel a and channel b lvds output data 2 complement. m8 d3+ab output channel a and channel b lvds output data 3 true. l8 d3?ab output channel a and channel b lvds output data 3 complement. k9 d4+ab output channel a and channel b lvds output data 4 true. j9 d4?ab output channel a and channel b lvds output data 4 complement. agnd vin+c vin?c agnd avdd clk? clk+ avdd agnd vin?b vin+b ag nd 1 2 3 4 5 6 7 8 9 10 11 12 agnd agnd vcmc agnd avdd avdd avdd avdd agnd vcmb agnd agnd vin+d agnd agnd csb sdio sclk pdwn sync mode agnd agnd vin+a vin?d vcmd agnd avdd avdd avdd av dd avdd avdd agnd vcma vin?a agnd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drgnd drvdd drv dd drvdd drvdd drvdd drvdd drvdd drvdd drvdd drvdd drvdd drvdd d0?cd d2?cd d4?cd d6?cd d8?cd d10?cd d0?ab d2?ab d4?ab d6?ab d8?ab d10?ab d0+cd k d2+cd d4+cd d6+cd d8+cd d10+cd d0+ab d2+ab d4+ab d6+ab d8+ab d10+ab d1?cd d3?cd d5?cd d7?cd d9?cd dco?cd d1?ab d3?ab d5?ab d7?ab d9?ab dco?ab d1+cd a b c d e f g h j l m d3+cd d5+cd d7+cd d9+cd dco+cd d1+ab d3+ab d5+ab d7+ab d9+ab dco+ab 09684-004
data sheet AD6657A rev. 0 | page 13 of 36 pin no. mnemonic type description m9 d5+ab output channel a and channel b lvds output data 5 true. l9 d5?ab output channel a and channel b lvds output data 5 complement. k10 d6+ab output channel a and channel b lvds output data 6 true. j10 d6?ab output channel a and channel b lvds output data 6 complement. m10 d7+ab output channel a and channel b lvds output data 7 true. l10 d7?ab output channel a and channel b lvds output data 7 complement. k11 d8+ab output channel a and channel b lvds output data 8 true. j11 d8?ab output channel a and channel b lvds output data 8 complement. m11 d9+ab output channel a and channel b lvds output data 9 true. l11 d9?ab output channel a and channel b lvds output data 9 complement. k12 d10+ab output channel a and channel b lvds output data 10 true. j12 d10?ab output channel a and channel b lvds output data 10 complement. m12 dco+ab output data clock lvds output for channel a and channel b true. l12 dco?ab output data clock lvds output for channel a and channel b complement. k1 d0+cd output channel c and channel d lvds output data 0 true. j1 d0?cd output channel c and channel d lvds output data 0 complement. m1 d1+cd output channel c and channel d lvds output data 1 true. l1 d1?cd output channel c and channel d lvds output data 1 complement. k2 d2+cd output channel c and channel d lvds output data 2 true. j2 d2?cd output channel c and channel d lvds output data 2 complement. m2 d3+cd output channel c and channel d lvds output data 3 true. l2 d3?cd output channel c and channel d lvds output data 3 complement. k3 d4+cd output channel c and channel d lvds output data 4 true. j3 d4?cd output channel c and channel d lvds output data 4 complement. m3 d5+cd output channel c and channel d lvds output data 5 true. l3 d5?cd output channel c and channel d lvds output data 5 complement. k4 d6+cd output channel c and channel d lvds output data 6 true. j4 d6?cd output channel c and channel d lvds output data 6 complement. m4 d7+cd output channel c and channel d lvds output data 7 true. l4 d7?cd output channel c and channel d lvds output data 7 complement. k5 d8+cd output channel c and channel d lvds output data 8 true. j5 d8?cd output channel c and channel d lvds output data 8 complement. m5 d9+cd output channel c and channel d lvds output data 9 true. l5 d9?cd output channel c and channel d lvds output data 9 complement. k6 d10+cd output channel c and channel d lvds output data 10 true. j6 d10?cd output channel c and channel d lvds output data 10 complement. m6 dco+cd output data clock lvds output for channel c and channel d true. l6 dco?cd output data clock lvds output for channel c and channel d complement. c9 mode input mode select pin. logic low enables nsr; logic high disables nsr. c8 sync input digital synchronization pin. c7 pdwn input power - down input (active high). c6 sclk input spi clock. c5 sdio input/output spi data. c4 csb input spi chip select (active low).
AD6657A data sheet rev. 0 | page 14 of 36 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = 185 msps, 1.75 v p - p differential input, vin = ?1.0 dbfs, 32,000 sample, t a = 25c, unless otherwise noted. figure 5 . single tone fft, f in = 10.3 mhz figure 6 . single tone fft, f in = 50.3 mhz figure 7 . single tone fft, f in = 70. 3 mhz figure 8 . single tone fft, f in = 140.3 mhz figure 9 . single tone fft, f in = 200.3 mhz figure 10 . single tone fft, f in = 230.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic s econd harmonic amplitude (dbfs) 09684-005 185msps 10.3mhz @ ?1dbfs snr = 65.6db (66.6dbfs) sfdr = 94.0dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic second harmonic amplitude (dbfs) 09684-006 185msps 50.3mhz @ ?1dbfs snr = 65.6db (66.6dbfs) sfdr = 92.0dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic s econd harmonic amplitude (dbfs) 09684-007 185msps 70.3mhz @ ?1dbfs snr = 65.5db (66.5dbfs) sfdr = 88dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic s econd harmonic amplitude (dbfs) 09684-008 185msps 140.3mhz @ ?1dbfs snr = 65.4db (66.4dbfs) sfdr = 90dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic second harmonic amplitude (dbfs) 09684-009 185msps 200.3mhz @ ?1dbfs snr = 64.9db (65.9dbfs) sfdr = 84dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic s econd harmonic amplitude (dbfs) 09684-010 185msps 230.3mhz @ ?1dbfs snr = 66.1db (65.1dbfs) sfdr = 84dbc
data sheet AD6657A rev. 0 | page 15 of 36 figure 11 . single tone fft, f in = 247.3 mhz figure 12 . single tone fft, f in = 305.3 mhz figure 13 . single tone fft, f in = 140.3 mhz, nsr enabled in 22% bw mode, tuning word = 28 figure 14 . single tone fft, f in = 230.3 mhz, nsr enabled in 33% bw mode, tuning word = 17 figure 15 . single tone fft, f in = 230.3 mhz, nsr enabled in 36% bw mode, tuning word = 14 figure 16 . single tone snr/sfdr vs. input amplitude (a in ), f in = 70.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic s econd harmonic amplitude (dbfs) 09684-011 185msps 247.3mhz @ ?1dbfs snr = 66db (65dbfs) sfdr = 83dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) third harmonic second harmonic amplitude (dbfs) 09684-012 185msps 305.3mhz @ ?1dbfs snr = 64.9db (65.9dbfs) sfdr = 80dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 f requency (mhz) third harmonic amplitude (dbfs) 09684-013 185msps 140.3mhz @ ?1dbfs nsr 22% bw mode, tw = 28 snr = 73.4db (74.9dbfs) sfdr = 91dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 f requency (mhz) third harmonic second harmonic amplitude (dbfs) 09684-014 185msps 230.3mhz @ ?1dbfs nsr 33% bw mode, tw = 17 snr = 70.8db (72.5dbfs) sfdr = 93.7dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-015 185msps 230.3mhz @ ?1dbfs nsr 36% bw mode, tw = 14 snr = 70.3db (71.3dbfs) sfdr = 93.4dbc third harmonic 100 90 80 70 60 50 40 30 20 10 0 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09684-016 snr (dbc) sfdr (dbc) snr (dbfs) sfdr (dbfs)
AD6657A data sheet rev. 0 | page 16 of 36 figure 17 . single tone snr/sfdr vs. input amplitude (a in ), f in = 140.3 mhz figure 18 . single tone snr/sfdr vs. input frequency (f in ), 1.75 v p - p full scale figure 19 . single tone snr/sfdr vs. input frequency (f in ), 2.0 v p - p full scale figure 20 . single tone snr/sfdr vs. sample rate (f s ), f in = 70.3 mhz figure 21 . single tone snr/sfdr vs. sample rate (f s ), f in = 140.3 mhz figure 22 . two tone fft, f in1 = 169.1 mhz and f in2 = 172.1 mhz 100 90 80 70 60 50 40 30 20 10 0 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09684-017 snr (dbc) sfdr (dbc) snr (dbfs) sfdr (dbfs) 95 90 85 80 75 70 65 60 400 380 360 340 320 300 160 140 120 100 80 60 280 260 240 220 200 180 input frequency (mhz) snr/sfdr (dbfs and dbc) 09684-018 snr (dbfs) sfdr (dbc) 95 90 85 80 75 70 65 60 400 380 360 340 320 300 160 140 120 100 80 60 280 260 240 220 200 180 input frequency (mhz) snr/sfdr (dbfs and dbc) 09684-019 snr (dbfs) sfdr (dbc) 100 95 90 85 80 75 70 65 60 55 50 30. 00 51.25 72.50 93.75 115.00 136.25 157.50 178.75 200.00 sample rate (msps) snr/sfdr (dbfs and dbc) 09684-020 snr (dbfs) sfdr (dbc) 95 90 85 80 75 70 65 60 55 50 30. 00 51.25 72.50 93.75 115.00 136.25 157.50 178.75 200.00 sample rate (msps) snr/sfdr (dbfs and dbc) 09684-021 snr (dbfs) sfdr (dbc) 0 ?20 ?40 ?60 ?80 ?100 ?120 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-122 185msps 169.1mhz @ ?7dbfs 172.1mhz @ ?7dbfs sfdr = 88.5dbc
data sheet AD6657A rev. 0 | page 17 of 36 figure 23 . two tone sfdr/imd3 vs. input amplitude (a in ), f in1 = 169.1 mhz and f in2 = 172.1 mhz figure 24 . grounded input histogram figure 25 . inl, f in = 30.3 mhz figure 26 . dnl, f in = 30.3 mhz figure 27 . snr vs. duty cycle, f in = 10.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09684-123 imd3 (dbfs) sfdr (dbfs) imd3 (dbc) sfdr (dbc) 2,500,000 2,000,000 1,500,000 1,000,000 500,000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 output code number of hits 09684-124 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 output code inl error (lsb) 09684-125 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 0 500 1000 1500 2000 output code dnl error (lsb) 09684-126 69 68 67 66 65 64 63 62 61 60 30 35 40 45 50 55 60 65 70 duty cycle (%) snr (dbfs) 09684-127
AD6657A data sheet rev. 0 | page 18 of 36 equivalent circuits figure 28 . equivalent analog input circuit figure 29 . equivalent clock input circuit figure 30 . equivalent lvds output circuit figure 31 . equivalent sync input circuit figure 32 . equivalent sclk and pdwn input circuit figure 33 . equivalent csb and mode input circuit figure 34 . equivalent sdio circuit vin avdd 09684-022 0.9v 15k? 15k? clk+ clk? avdd 09684-023 avdd avdd 09684-024 dr vdd da taout+ v? v+ da taout? v+ v? avdd avdd 16k? 0.9v 0.9v sync 08557-025 sclk or pdwn 350 ? 30 k? 09684-026 csb or mode 350 ? 30 k? avdd 09684-027 sdio 350? 30k? drvdd 09684-028
data sheet AD6657A rev. 0 | page 19 of 36 theory of operation adc architecture the AD6657A architecture consists of a quad front - end sample - and - hold circuit, followed by a pipelined, switched capacitor adc. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. alternately, the 14 - bit result can be processed through the nsr block before it is sent to the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor digital - to - analog converter (dac) and an interstage residue amplifier (mdac). the residue amplifier ma gnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powere d from a separate supply, allowing adjustment of the output drive current. during power - down, the output buffers go into a high impedance state. the AD6657A quad if receiver can simultaneously digitize four channels, making it ideal for diversity reception and digital pre - disto rtion (dpd) observation paths in telecommunication systems . synchronization capability is provided to allow synchronized timing between multiple channels or multiple dev ices. programming and control of the AD6657A are accomplished using a 3 - wire spi - compatible serial interface. analog input considerations the analog input to the ad 6657a is a differential switched capacitor circuit that has been designed for optimum perfor - mance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see figure 35 ). when the input is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a lo w- pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, any shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. for more information on this subject, see the an - 742 application note , frequency domain response of switched - capacitor adcs ; an -8 27 application note , a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article, transformer - coupled front - end for wideband a/d converters (see www.analog.com ). figure 35 . switched capacitor input for best dynamic performance, match the source impedances driving the vin+ and vin? pins. an internal differential reference buffer creates positive and negative reference voltages that define th e input span of the adc core. the span of the adc core is set by this buffer to 2 v ref . input common mode the analog inputs of the AD6657A are not internally dc biased. in ac - coupled applications, the user must provide this bias externally. an on - board common - mode voltage reference is included in the design and is available from the vcmx pins. optimum performance is achieved when the common - mode voltage of the analog input is set by the vcmx pin voltage (typically 0.5 avdd). the vcmx pins must be decoupled to ground by a 0.1 f capacitor. c par1 c par1 c par2 c par2 s s s s s s c fb c fb c s c s bias bias vin+ h vin? 09684-029
AD6657A data sheet rev. 0 | page 20 of 36 differential input configurations optimum performance is achieved when driving the AD6657A in a differential input configuration. for baseband applications, the ad8138 , ada4937 -2 , and ada4938 -2 differential drivers provide excellent performance and a flexible interface to the adc. the output common - mode voltage of the ada4938 -2 is easily set with the vcmx pin of the AD6657A (see figure 36 ), and the driver can be configured in a sallen - key filter topology to provide band limiting of the input signal. figure 36 . differential input configuration using the ada4938 - 2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an e xample is shown in figure 37 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer . figure 37 . differential transformer - coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD6657A . for applications in which snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 38 ). in this configuration, the input is ac - coupled and the cml is provided to each input through a 33 ? resistor. these resistors compensate for losses in the input baluns to provide a 50 ? imp edance to the driver. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or removed. table 10 lists recommended values to set the rc network. at higher input frequencies, good performance can be achieved by using a ferrite bead in series with a resistor and removing the ca pacitors. however, these values are dependent on the input signal and should be used as a starting guide only. table 10 . example rc network freuency range m r1 series eac c1 differential r2 series eac c2 sunt eac 0 to 100 33 5 pf 15 15 pf 100 to 200 10 5 pf 10 10 pf 100 to 300 10 1 remove 66 remove 1 in this configuration, r1 is a ferrite bead with a value of 10 @ 100 mhz. an alternative to using a transformer - coupled input at frequen - cies in the second nyquist zone is to use the ad8352 differential driver (see figure 39 ). for more information, see the ad8352 data sheet. figure 38 . differential double balun input configuration figure 39 . differential input configuration using the ad8352 vin 76.8? 120? 0.1f 200? 200? 90? avdd 33? 33? 15? 15? 5pf 15pf 15pf adc vin? vin+ vcm ada4938-2 09684-030 2v p-p 49.9? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r2 c2 09684-031 adc r1 0.1f 0.1f 2v p-p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33? 33? s p a p 09684-032 ad8352 0? 0? 0.1f 0.1f 0.1f 0.1f 16 1 2 5 11 0.1f 0.1f 10 14 0.1f 8, 13 v cc 200? 200? analog input analog input c r adc vin+ vin? vcm r 4 3 09684-033 r g r d c d
data sheet AD6657A rev. 0 | page 21 of 36 figure 40 . 1:4 transformer passive configuration figure 41 . active front - end configuration using the ad8376 for the popular if band of 140 mhz, figure 40 shows an example of a 1:4 transformer passive configuration where a differential inductor is used to resonate with the internal input capacitance of the AD6657A . this configuration realizes excellent noise and distortion performance. figure 41 shows an example of an active front - end configuration using the ad8376 dual vari - able gain amplifi er (vga). this configuration is recommended when signal gain is required. clock input considerations for optimum performance, clock the AD6657A sample clock inputs, clk+ and clk?, with a differential signal. th e signal is typically ac - coupled into the clk+ and clk? pins via a trans - former or capacitors. these pins are biased internally and require no external bias (see figure 42). figure 42 . equivalent clock input circuit clock input options the AD6657A has a very flexible clock input structure. the clock input can be a cmos, lvds, lvpecl , or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern (see the jitter considerations section ). figure 43 and figure 44 show two preferred methods for clocking the AD6657A (at clock rates of up to 625 mhz). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf balun or an rf transformer. the rf balun configuration is recommended for clock fr equencies between 125 mhz and 625 mhz, and the rf transformer config - uration is recommended for clock frequencies from 10 mhz to 200 mhz. the back - to - back schottky diodes across the trans - former/balun secondary limit clock excursions into the AD6657A to ap proximately 0.8 v p - p differential. this limit helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD6657A , yet preserves the fast rise and fall times of the signal that are critical to a low jitter performance. figure 43 . transformer - coupled differential clock (up to 200 mhz) figure 44 . balun - coupled differential clock (up to 625 mhz) 431nh vcm adc interna l input z analog input xfmr 1:4 z etc4-1 t-7 input z = 50? 3.0pf 3.0k? 33? 121? 121? 33? 0.1f 0.1f 0.1f 0.1f 0.1f 09684-034 ad8376 ad6657 a 1h 1h 1nf 1nf vpos vcm 15pf 68nh 3.0k?U3.0pf 301? 165? 165? 5.1pf 3.9pf 180nh 1000pf 1000pf notes 1. al l induc t ors are coilcraft 0603cs components with the exception of the 1h choke induc t ors (0603ls). 180nh 220nh 220nh 09684-035 1.2v avdd 2pf 2pf clk? clk+ 09684-036 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc adt1-1wt, 1:1z xfmr 09684-037 0.1f 0.1f 1nf clock input 1nf 50? clk? clk+ schottky diodes: hsms2822 adc 09684-038
AD6657A data sheet rev. 0 | page 22 of 36 if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 45 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 clock drivers offer excellent jitter performance. figure 45 . differential pecl sample clock (up to 625 mhz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 46 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 clock drivers offer excellent jitter performance. figure 46 . differential lvds sample clock (up to 625 mhz) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applica - tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 47). figure 47 . single - ended 1.8 v cmos input clock (up to 200 mhz) clk+ can be driven directly from a cmos gate. although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages of up to 3.6 v, making the selection of the drive logic voltage very flexible (see figure 48 ). figure 48 . single - ended 3.3 v cmos input clock (up to 200 mhz) input clock divider the AD6657A contains an input clock divider with the ability to divide the input clock by integer values from 1 to 8. the AD6657A clock divider can be synchronized using the external sync input. bit 1 of register 0x3a enables the clock divider to be resynchronized on every sync signal. a valid sync causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic perfor - mance characteristics. the AD6657A contains a dcs that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows th e user to provide a wide range of clock input duty cycles without affecting the performance of the AD6657A . noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs enabled. jitter in the rising edge of the input is of paramount concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates at less than 40 mhz nominally. the loop ha s a time constant assoc iated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed , and internal device timing is dependent on the duty cycle of the input clock signal. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? pecl driver 50k? 50k? clk? clk+ clock input clock input ad951x adc 09684-039 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 09684-040 optional 100? 0.1f 0.1f 0.1f 39k? 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 09684-041 1 50? resistor is optional. optional 100? 0.1f 0.1f 0.1f v cc 50? 1 clk? clk+ adc 1k? 1k? clock input ad951x cmos driver 09684-042
data sheet AD6657A rev. 0 | page 23 of 36 jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock in put. the degradation in snr from the low frequency snr (snr lf ) at a given input frequency ( f in ) due to jitter ( t jrms ) can be calculated by snr hf = ?10log[(2 f in t jrms ) 2 + 10 (?snr lf /10) ] in the equation, the rms aperture jitter represents the clock in put jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 49. figure 49 . snr vs. input frequency and jitter in cases where aperture jitter may affect the dynamic range of the AD6657A , treat the clock input as an analog signal. separate power supplies for c lock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to the an - 501 applic ation note and an - 756 application note for more informa - tion about jitter performance as it relates to adcs (available at www.analog.com ). power dissipation an d standby mode the power dissipated by the AD6657A is proportional to its clock rate (see figure 50 ). the digital power dissipation does not vary significantly because it is determined primarily by the drvdd supply and the bias current of the lvds drivers. reducing the capacitive load presented to the output drivers can minimize digital power consumption. the data in figure 50 was obtained using the same operating conditions as those used in the typical performance characteristics section, with a 5 pf load on each output driver. figure 50 . power and current vs. sampling frequency by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the AD6657A is placed in power - down mode. in this state, the adc typically dissipates 4.5 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD6657A to i ts normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing net works, and clock. internal capacitors are discharged when entering power - down mode and must be recharged when returning to normal operation. as a result, wake - up time is related to the time spent in power - down mode; shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see th e memory map register descriptions section for more details. channel/chip synchro niation the AD6657A has a sync input that offers the user flexible synchroni zation options for syn chronizing the clock divider. the clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple adcs. the sync input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty b etween multiple parts, externally synchronize the sync input signal to the input clock signal, meeting the setup and hold times shown in table 5 . driv e the sync input using a single - ended cmos type signal. 80 75 70 65 60 55 50 1 10 100 1k i nput frequency (mhz) snr (dbc) 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps 09684-043 1.5 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0. 25 0.20 0.15 0.10 0.05 0 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 sampling frequency (msps) 200 total power (w) current (a) 09684-050 i avdd i drvdd total power
AD6657A data sheet rev. 0 | page 24 of 36 digital outputs the AD6657A output drivers are configured to interface with lvds outputs using a drvdd supply voltage of 1.8 v. the output bits are ddr lvds as shown in figure 2 . applications that require the adc to drive large capacitive loads or large fanouts may require external buffers or latches . as described in the an - 877 application note , interfacing to high speed adcs via spi , the data format can be selected for offset binary or twos complement when using the spi control. timing the AD6657A provides latched data with a latency of nine clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. minimize the length of the output data lines and minimize the loads placed on them to reduce transients within th e AD6657A because these transients can degrade converter dynamic per - formance. the lowest typical conversion rate of the AD6657A is 40 msps. at clock rates below 40 msps, dynamic performance can degrade. data clock output (dco) the AD6657A provides a data clock output (dco) signal intended for capturing the data in an ex ternal register. the output data for channel a and channel c is valid when dco is high; the output data for channel b and channel d is valid when dco is low (see figure 2 ). table 11 . output data format input (v) condition (v) offset binary output mode twos complement mode vin+ ? vin? < ?v ref ? 0.5 lsb 000 0000 0000 100 0000 0000 vin+ ? vin? = ?v ref 000 0000 0000 100 0000 0000 vin+ ? vin? = 0 100 0000 0000 000 0000 0000 vin+ ? vin? = +v ref ? 1.0 lsb 111 1111 1111 011 1111 1111 vin+ ? vin? > +v ref ? 0.5 lsb 111 1111 1111 011 1111 1111
data sheet AD6657A rev. 0 | page 25 of 36 noise shaping requan tizer the AD6657A features a noise shaping requantizer (nsr) to allow higher than an 11 - bit snr to be maintained in a subset of the nyquist band. the harmonic performance of the receiver is unaffected by the nsr feature. when enabled, the nsr contributes an additional 0.6 db of loss to the input signal, such that a 0 dbfs input is reduced to ?0.6 dbfs at the output pins. the nsr feature can be independently controlled per channel via the spi or via the mode pin. two different bandwidth modes are provided; the mode can be selected from the spi port. in each of the two modes, the center frequency of the band can be tuned such that ifs can be pl aced anywhere in the nyquist band. 22% bw mode (>40 mhz at 184.32 msps) the first bandwidth mode offers excellent noise performance over 22% of the adc sample rate (44% of the nyquist band) and can be centered by setting the nsr mode bits in the nsr contro l register (address 0x3c) to 000. in this mode, the useful frequency range can be set using the 6 - bit tuning word in the nsr tuning word register (address 0x3e). there are 57 possible tuning words (tw); each step is 0.5% of the adc sample rate. the follow ing three equations describe the left band edge (f 0 ), the channel center (f center ), and the right band edge (f 1 ), respectively. f 0 = f adc .005 tw f center = f 0 + 0.11 f adc f 1 = f 0 + 0.22 f adc figure 51 to figure 53 show the typical spectrum that can be expected from the AD6657A in the 22% bw mode for three different tuning words. figure 51 . 22% bw mode, tuning word = 13 figure 52 . 22% bw mode, tuning word = 28 (f s /4 tuning) figure 53 . 22% bw mode, tuning word = 41 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-051 185msps 140.3mhz @ ?1dbfs nsr 22% bw mode, tw = 13 snr = 73.4db (75.0dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-052 185msps 140.3mhz @ ?1dbfs nsr 22% bw mode, tw = 28 snr = 73.4db (75.0dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-053 185msps 140.3mhz @ ?1dbfs nsr 22% bw mode, tw = 41 snr = 73.4db (75.0dbfs) sfdr = 91dbc third harmonic
AD6657A data sheet rev. 0 | page 26 of 36 33% bw mode (>60 mhz at 184.32 msps) the second bandwidth mode offers excellent noise performance over 33% of the adc sample rate (66% of the nyquist band) and can be centered by setting the nsr mode bits in the nsr control register (address 0x3c) to 001. in this mode, the useful frequency range can be set using the 6 - bit tuning word in the nsr tuning word register (address 0x3e). there are 34 possible tuning words (tw) ; each step is 0.5% of the adc sample rate. the following three equations describe the left band edge (f 0 ), the channel center (f center ), and the right band edge (f 1 ), respectively. f 0 = f adc .005 tw f center = f 0 + 0.165 f adc f 1 = f 0 + 0.33 f adc figure 54 to figure 56 show the typical spectrum that can be expected from the AD6657A in the 33% bw mode for three different tuning words. figure 54 . 33% bw mode, tuning word = 5 figure 55 . 33% bw mode, tuning word = 17 (f s /4 tuning) figure 56 . 33% bw mode, tuning word = 17 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-154 185msps 140.3mhz @ ?1dbfs nsr 33% bw mode, tw = 5 snr = 70.9db (72.5dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-055 185msps 140.3mhz @ ?1dbfs nsr 33% bw mode, tw = 17 snr = 71.1db (72.7dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-056 185msps 140.3mhz @ ?1dbfs nsr 33% bw mode, tw = 17 snr = 70.9db (72.5dbfs) sfdr = 91dbc third harmonic
data sheet AD6657A rev. 0 | page 27 of 36 36% bw mode (>65 mhz at 184.32 msps) the third bandwidth mode offers excellent noise performance over 36% of the adc sample rate (72% of the nyquist band) and can be centered by setting the nsr mode bits in the nsr control register (address 0x3c) to 010. in this mode, the useful frequency range can be set using the 6 - bit tuning word in the nsr tuning register (address 0x3e). there are 28 possible tuning words (tw); each step is 0.5% of the adc sample rate. the following three equations describe the left band edge (f 0 ), the channel center (f center ), and the right band edge (f 1 ), respectively. f 0 = f adc .005 tw f center = f 0 + 0.18 f adc f 1 = f 0 + 0.36 f adc figure 57 to figure 59 show the typical spectrum that can be expected from the AD6657A in the 36% bw mode for three different tuning words. figure 57 . 36% bw mode, tuning word = 0 figure 58 . 36% bw mode, tuning word = 14 (f s /4 tuning) figure 59 . 36% bw mode, tuning word = 28 mode pin the mode pin input allows convenient control of the nsr feature. a logic low enables nsr mode and a logic high sets the receiver to a straight 11 - bit mode with nsr disabled. by default, the mode pin is pulled high internally to disable the nsr. each channel can be individually configured to ignore the mode pin state by writing to bit 4 of the nsr control register at address 0x3c. use of the nsr control register in conjunction with the mode pin allows for very flexible control of the nsr feature on a per channel basis. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-057 185msps 140.3mhz @ ?1dbfs nsr 36% bw mode, tw = 0 snr = 70.4db (72.0dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9. 25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) amplitude (dbfs) 09684-058 185msps 140.3mhz @ ?1dbfs nsr 36% bw mode, tw = 14 snr = 70.4db (72.0dbfs) sfdr = 91dbc third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 frequency (mhz) t hird harmonic amplitude (dbfs) 09684-059 185msps 140.3mhz @ ?1dbfs nsr 36% bw mode, tw = 28 snr = 70.4db (72.0dbfs) sfdr = 91dbc
AD6657A data sheet rev. 0 | page 28 of 36 built - in self test (bist) and output test the AD6657A includes built - in test features designed to v erify the integrity of each channel and to facilitate board - level debug - ging. a built - in self test ( bist ) feature is included that verifies the integrity of the digital datapath of the AD6657A . various output t est options are also provided to place predictable values on the outputs of the AD6657A . bist the bist is a thorough test of the digital portion of the selected AD6657A signal path. when enabled, the test runs from an internal pseudorandom noise (pn) source through the digital datapath starting at the adc block output. the bist sequence runs for 512 cycles and stops. the bist signature value for the selected chann el is written to register 0x24 and register 0x25. if more than one channel is bist enabled, the channel that is first according to alphabetical order is written to the bist signature registers. for example, if channel b and channel c are bist enabled, th e results from channel b are written to the bist signature registers. the outputs are not disconnected during this test, so the pn sequence can be observed as it runs. the pn sequence can be continued from its last value or reset from the beginning, based on the value programmed in register 0x0e, bit 2. the bist signature result varies based on the channel configuration. output test modes the output test options are shown in table 13 . when an output test mode is enabled, the analog section of the receiver is dis - connected from the digital back - end blocks, and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting. the seed value for the pn sequence tests can be forced if the pn reset bits are used to hold the generator in reset mode by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they require an encode clock. for more information, see the an - 877 application note , interfacing to high speed adcs via spi .
data sheet AD6657A rev. 0 | page 29 of 36 serial port interface (spi) the AD6657A serial port interface (spi) allows the user to con - figure the receiver for specific functions or operations through a structured internal register space. the spi provides added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which ar e documented in the memory map section. for detailed operational information, see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of the AD6657A : sclk, sdio, and csb (see table 12 ). sclk (a serial clock) is used to synchronize the read and write data presented from and to the AD6657A . sdio (serial data input/output) is a bidirectional pin that allows data to be sent to and read from the internal memory map registers. csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 12 . serial port interface pins pin function sclk serial clock. serial shift clock input. sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. bidirectional pin that serves as an input or an output, depending on the instruction being sent and the relative positio n in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb pin, in conjunction with the rising edge of the sclk pin, determines the start of the framing. an example of the serial timing can be found in figure 60 (for symbol definitions, see table 5 ). csb can be held low indefinitely, which permanently enables the device; this is called streaming. csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. during an instruction phase, a 16 - bit instruction is transmitted. the first bit of the firs t byte in a serial data transfer frame indicates whether a read command or a write command is issued. data follows the instruction phase, and its length is determined by the w0 and w1 bits. all data is composed of 8 - bit words. the instruction phase determ ines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a read operation, the serial data input/output (sdio) pin changes direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default mode on power - up and can be changed via the spi port configuration register. for more info rmation about this and other features, see the an - 877 application note , inter - facing to high speed adcs via spi . hardware interface the pins described in table 12 constitute the physical interface between the users programming device and the serial port of the AD6657A . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during the write phase and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in application note an - 812, micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performa nce of the AD6657A is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade AD6657A performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6657A to prevent these signals from transi - tioning at the rec eiver inputs during critical sampling periods. figure 60 . serial port interface timing diagram don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09684-054
AD6657A data sheet rev. 0 | page 30 of 36 memory map reading the memory map register table each row in the memory map register table has eight bit loca- tions (see table 13). the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 and address 0x01); the channel index and transfer registers (address 0x05 and address 0xff); the adc function registers, including setup, control, and test (address 0x08 to address 0x25); and the digital feature control registers (address 0x3a to address 0x3e). the memory map register table (see table 13) provides the default hexadecimal value for each hexadecimal address shown. the column with the heading (msb) bit 7 is the start of the default hexadecimal value given. the an-877 application note , interfacing to high speed adcs via spi , documents the functions controlled by register 0x00 to register 0xff. the remaining registers, register 0x3a to register 0x3e, are documented in the memory map register descriptions section. open locations all address and bit locations that are not included in table 13 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the AD6657A is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table (see table 13). logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x3e are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, thereby setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the transfer bit is autoclearing. channel specific registers some channel setup functions, such as the nsr control func- tion, can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 13 as local. local registers and bits can be accessed by setting the appropriate channel bits in register 0x05. if multiple channel bits are set, the subsequent write affects the registers of all selected channels. in a read cycle, select a single channel only to read one of the registers. if multiple channels are selected during a spi read cycle, the device returns the value for channel a only. registers and bits designated as global in table 13 affect the entire device or the channel features for which there are no independent per channel settings. the settings in register 0x05 do not affect the global registers and bits.
data sheet AD6657A rev. 0 | page 31 of 36 memory map register table all address and bit locations that are not included in table 13 are not currently supported for this device. table 13 . memory map registers addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments chip configuration registers 0x00 spi port configuration (global) open lsb first soft reset 1 1 soft reset lsb first open 0x18 nibbles are mirrored so that lsb first or msb first mode is set correctly, regardless of shift mode. to control this register, all channel index bits in register 0x05 must be set. 0x01 chip id (global) 8- bit chip id, bits[7:0] AD6657A = 0x7b (default) 0x7b read only. channel index and transfer registers 0x05 channel index enable output port for channel c and channel d enable output port for channel a and channel b open open channel d enable channel c enable channel b enable channel a enable 0xcf bits are set to determine which channel on the chip receives the next write command; applies to local registers. 0x ff transfer open open open open open open open sw transfer 1 = on 0 = off (default) 0x00 synchro - nously transfers data from the master shift register to the slave. adc function registers 0x08 power modes open open external power - down pin function (global) 0 = full power - down 1 = standby open open open internal power - down mode (local) 00 = normal operation (default) 01 = full power - down 10 = standby 0x00 determines generic modes of chip opera - tion. 0x0b clock divide (global) open open clock divide phase 000 = 0 input clock cycles delayed 001 = 1 input clock cycle delayed 010 = 2 input clock cycles delayed clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 0x0c shuffle mode (local) open open open open open open shuffle mode enable 00 = shuffle disabled 01 = shuffle enabled 0x01 enables or disables shuffle mode.
AD6657A data sheet rev. 0 | page 32 of 36 addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments 0x0d test mode (local) open open reset long pn generator 0 = on 1 = off (default) reset short pn generator 0 = on 1 = off (default) open output test mode 000 = off (normal operation) 001 = midscale short 010 = positive fs 011 = negative fs 100 = alternating checkerboard 101 = pn sequence long 110 = pn sequence short 111 = 1/0 word toggle 0x00 when set, the test data is placed on the output pins in place of normal data. 0x0e bist enable (local) open open open open open bist reset 0 = on 1 = off (default) open bist enable 1 = on 0 = off (default) 0x00 when bi t 0 is set, the built - in self test function is initiated. 0x10 offset adjust (local) open open offset adjustment in lsbs from +127 to ?128 (twos complement format) 011111 = +31 lsb 011110 = +30 lsb 011101 = +29 lsb 000010 = +2 lsb 000001 = +1 lsb 000000 = 0 lsb 111111 = ?1 lsb 111110 = ?2 lsb 111101 = ?3 lsb 100001 = ?31 lsb 100000 = ?32 lsb 0x00 device offset trim. 0x14 output mode (local) open open open output enable bar (local) 1 = off 0 = on open output invert (local) 1 = on 0 = off output format (local) 00 = offset binary 01 = twos complement 0x00 configures the outputs and the format of the data. 0x15 output adjust (local) open open open open output port lvds drive current 0000 = 3.72 ma 0001 = 3.5 ma (default) 0010 = 3.3 ma 0011 = 2.96 ma 0100 = 2.82 ma 0101 = 2.57 ma 0110 = 2.27 ma 011 1 = 2.0 ma 1000 = 2.0 ma 0x01 output current adjustments. 0x16 clock phase control (local) invert dco clock 0 = off 1 = on open open open open open open open 0x00 when bit 7 is set, clock polarity is reversed. 0x17 dco output delay (local) dco delay enable 0 = off 1 = on open open output port dco clock delay 00000 = 100 ps additional delay on the dco pin 00001 = 200 ps additional delay on the dco pin 00010 = 300 ps additional delay on the dco pin 11101 = 3.0 ns additional delay on the dco pin 11110 = 3.1 ns additional delay on the dco pin 11111 = 3.2 ns additional delay on the dco pin 0x00 enable dco delay and set the delay time. 0x18 v ref select (global) open open open internal v ref full - scale adjustment main reference full - scale v ref adjustment 01111: internal 2.087 v p -p 00001: internal 1.772 v p -p 00000: internal 1.75 v p -p 11111: internal 1.727 v p - p 10000: internal 1.383 v p -p 0x00 select adjustments for v ref .
data sheet AD6657A rev. 0 | page 33 of 36 addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments 0x24 bist signature lsb (local) bist signature[7:0] 0x00 read only. 0x25 bist signa - ture msb (local) bist signature[15:8] 0x00 read only. digital feature control registers 0x3a sync control (global) open open open open open clock divider s ync mode 0 = conti - nuous 1 = next sync mode, next rising edge of sync resets clock divider clock divider sync enable 0 = off 1 = on master sync enable 0 = off 1 = on 0x00 control register to synchronize the clock divider. 0x3c nsr control (local) open open open mode pin disable 0 = mode pin used 1 = mode pin dis - abled nsr mode 000 = 22% bw mode 001 = 33% bw mode 010 = 36% bw mode nsr enable 0 = off 1 = on (used only if bit 4 = 1; otherwise ignored) 0x00 noise shaping requantizer (nsr) controls. 0x3e nsr tuning word (local) open open nsr tuning word see the noise shaping requantizer section. equations for the tuning word are dependent on the nsr mode. 0x1c nsr frequency tuning word. memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed ad cs via spi . sync control (register 0x3a) its3 reserved it clock divider sync mode bit 2 selects the mode of the clock divider sync function. when bit 2 is low, continuous sync mode is enabled. when bit 2 is high, the clock divider is reset on the next rising edge of the sync signal. subsequent rising edges of the sync signal are ignored. bit 1 clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0 master sync enable bit 0 must be high to enable any of the sync functions. if the sync capability is not used, this bit should remain low to conserve power. nsr control (register 0x3c) its reserved it mode pin disale bit 4 specifies whether the selected channels are to be controlled by the mode pin. local registers act on the channels that are selected by the channel index register (address 0x05). bits[3:1] nsr mode bits[3:1] determine the bandwidth (bw) mode of the nsr. whe n bits[3:1] are set to 000, the nsr is configured for a 22% bw mode that provides enhanced snr performance over 22% of the sample rate. when bits[3:1] are set to 001, the nsr is configured for a 33% bw mode that provides enhanced snr performance over 33% of the sample rate. when bits[3:1] are set to 010, the nsr is configured for a 36% bw mode that pro - vides enhanced snr performance over 36% of the sample rate. bit 0 nsr enable the nsr is enabled when bit 0 is high and disabled when bit 0 is low. bit 0 is i gnored unless the mode pin disable bit (bit 4) is set.
AD6657A data sheet rev. 0 | page 34 of 36 nsr tuning word (register 0x3e) bits[7:6] reserved bits[5:0] nsr tuning word the nsr tuning word sets the band edges of the nsr band. in 22% bw mode, there are 57 possible tuning words; in 33% bw mod e, there are 34 possible tuning words; in 36% bw mode, there are 28 possible tuning words. for either mode, each step represents 0.5% of the adc sample rate. for the equations used to calculate the tuning word based on the bw mode of operation, see the noise shaping requantizer section.
data sheet AD6657A rev. 0 | page 35 of 36 applications informa tion design guidelines before starting t he design and layout of the AD6657A in a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certa in pins. power and ground recommendations when connecting power to the AD6657A , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). the avdd and drvdd supplies should be isolated with separate decoupling capacitors. several different dec oupling capacitors can be used to cover both high and low frequencies. locate these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length . a sin gle pcb ground plane is sufficient when using the AD6657A . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. vcmx pins the vcmx pins are provided to set the common - mode level of the analog inputs. decouple the vcmx pins to ground with a 0.1 f capacitor, as shown in figure 37. spi port the spi port should not be active dur ing periods when the full dynamic performance of the AD6657A is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can d egrade AD6657A performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6657A to prevent th ese signals from transi - tioning at the receiver inputs during critical sampling periods.
AD6657A data sheet rev. 0 | page 36 of 36 packaging and ordering information outline dimensions figure 61 . 144 - ball chip scale package ball grid array [csp_bga] (bc- 144 - 1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD6657Abbcz ?4 0c to +85c 144- ball chip scale package ball grid array [csp_bga] bc -144-1 AD6657Abbczrl ?4 0c to +85c 144 - ball chip scale package ball grid array [csp_bga] bc - 144 - 1 AD6657Aebz evaluation board 1 z = rohs compliant part. * compliant w ith jedec standards mo-275-eeab-1 with exception to package height . 10-21-2010-b 0.80 0.60 ref a b c d e f g 910 8 1 112 7 56 4 23 1 bottom view 8.80 bsc sq h j k l m detail a top view detail a coplanarity 0 .20 0.50 0.45 0.40 * 1.40 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.25 min 0.65 min ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09684 -0- 10/11(0) www.analog.com/ AD6657A

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